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ds04-22420-3e fujitsu semiconductor data sheet assp communication control cmos fast-20 scsi protocol controller MB86606A n description the MB86606A is an intelligent scsi protocol controller (spc) conforming to the ansi (fast-20) standard and integrating a pci local bus interface function. the specification of scsi controller block is based on the mb86605s one which is a wide scsi protocol controller, but the device functions/features to achieve the fast-20 data transfer rate of maximum 40 mbyte/sec at 16-bit fast-20 scsi, such as the size of internal data register fifo, are larged on the MB86606A. as for the scsi bus pins, a totem pole type single-ended driver/ receiver is incorporated in the device so that it can drive the scsi bus directly. furthermore, the MB86606A is capable of connecting the external differential type driver/receiver. the scsi bus sequence is controlled by commands issued via the system interface. so, it supports sequential commands that perform the phase-to-phase sequences to reduce the overhead of systems sequence operations. as another key feature to reduce the system overhead, the device has a 2 kbytes user program memory to store the user program with the commands. due to this, all the scsi bus sequences including the data transfer can be performed automatically. as the system interface block, it incorporates a 32-bit pci local bus interface that easily realizes the scsi interface on the motherboards of pci bus based pcs and wss, in addition to a 16-bit separate mpu and dma buses. for the on-chip pci bus interface, the MB86606A also incorporates a 32-bit dma controller that is capable of supporting the scatter-gather function so that the data transfers can be controlled by both user program and the host system. the device is fabricated by the advanced cmos process and is housed in an 144-pin plastic quad flat package (suffix: -pmt2). n pac k ag e (fpt-144p-m08) 144 pin plastic lqfp
2 MB86606A n features scsi protocol controller block: ? operable as initiator and target ? wide and fast-20 data transfers synchronous transfer (max. 40 mbytes/s: up to 256 offset values can be set.) asynchronous transfer (max. 10 mbytes/s) ? 512-byte fifo register for data phase ? two types (send-only and receive-only) of 32-byte data buffers for message, command, and status phases (mcs buffers) ? on-chip totem pole type scsi single-ended driver/receiver ? supports external scsi differential driver/receiver connectivity ? on-chip memory to store transfer parameters for each id (up to 15 connected devices) ? on-chip 16-bit transfer block counter and 24-bit transfer byte counter maximum transfer byte : 1 tbyte at fixed length data transfer : 16 mbyte at variable length data transfer ? supports various control commands: sequential commands : can perform phase-to-phase sequential operations (functions only when issuing from a system side.) discrete commands : can perform any desired sequence to program in the user program memory data transfer commands : can program the transfer data length at the user program operation. ? on-chip direct control register for scam (scsi configured automatically) level-1 protocol ? supports multi selection/reselection responses selection and reselection responses can be done to plural ids. ? on-chip 2 kbyte user program memory two modes : 2 kbyte 1 bank and 1 kbyte 2 banks (while 1 kbyte 2 banks are selected, host system can access another bank even if the user program is executing.) access to user program : burst transfer via i/o access port : direct access to 2 kbyte user program memory (only for pci bus i/f mode) ? user selectable interrupt report unnecessary interrupt reports can be disabled depending on users applications to reduce a system isr overhead. ? two automatic receive modes initiator : can automatically receive information for new phase to which target switched target : can automatically receive attention condition generated by initiator ? automatic selection/reselection for command issues : automatically performs to receive msg/cmd to the selection/reselection request from partner device for user program operation : pauses the program currently executed and automatically jumps to the specified selection /reselection routine in response to the selection/reselection request from partner device. ? operation clock system clock: max. 40 mhz internal processor operating clock: max. 20 mhz (continued)
3 MB86606A (continued) system interface block: ? separate mpu and dma buses called 16-bit bus mode directly connectable to 68-series or 80-series mpu two transfer modes (program transfer and dma transfer (slave mode)) ? pci bus interface mode directly connectable to the 32-bit pci local bus. on-chip 32-bit dmac for pci bus master supports the perr&serr function supports the inta# interrupt signals max. 64 bytes burst transfer pci system clock: max. 33 mhz ? data bus parity and address bus parity (only for pci bus interface mode) generation/check function others ? compact 144-pin plastic quad flat package (lqfp, package suffix: Cpmt2) ? pin compatible with mb86605 ? supply voltage: 5v 5%
4 MB86606A n pin assignment ? 16-bit bus mode 1 5 10 15 20 25 30 35 105 100 95 90 85 80 75 ldboep v dd db12 db13 db14 db15 v ss udbp db0 db1 v ss db2 db3 db4 db5 v ss db6 db7 ldbp atn v ss bsy ack rst msg sel v ss c/d req i/o db8 v ss db9 db10 db11 v dd dmd9 v ss dmd8 dmd7 dmd6 v dd dmd5 v ss dmd4 dmd3 dmd2 v ss dmd1 dmd0 ldmdp v ss udp v dd d15 d14 v ss d13 d12 d11 v ss d10 d9 d8 d7 v ss v dd d6 d5 d4 v ss d3 (fpt-144p-m08) (top view) 40 45 50 55 60 65 70 d2 d1 d0 v ss ldp uds/bhe v dd lds/wr v ss r/w/rd cs1 cs0 v dd int a4 a3 v ss sclk a2 a1 a0 v ss mode1 mode0 s/dsel targ v dd init seloe v ss rstoe bsyoe dboe11 dboe10 dboe9 dboe8 144 140 135 130 125 120 115 110 index dmd10 dmd11 dmd12 dmd13 v ss dmd14 dmd15 v dd udmdp dmr/w/dmrd v ss dmlds/dmwr dmuds/dmbhe v dd dreq dack v ss reset tp dma0 dboe12 dboe13 v ss dboe14 dboe15 udboep dboe0 dboe1 v dd dboe2 dboe3 dboe4 v ss dboe5 dboe6 dboe7
5 MB86606A ? pci bus interface mode 1 5 10 15 20 25 30 35 105 100 95 90 85 80 75 ldboep v dd db12 db13 db14 db15 v ss udbp db0 db1 v ss db2 db3 db4 db5 v ss db6 db7 ldbp atn v ss bsy ack rst msg sel v ss c/d req i/o db8 v ss db9 db10 db11 v dd ad23 v ss ad22 ad21 ad20 v dd ad19 v ss ad18 ad17 ad16 v ss c/be2 frame irdy v ss trdy v dd devsel stop v ss perr par c/be1 v ss ad15 ad14 ad13 ad12 v ss v dd ad11 ad10 ad9 v ss ad8 (fpt-144p-m08) (top view) 40 45 50 55 60 65 70 140 135 130 125 120 115 110 c/be0 ad7 ad6 v ss ad5 ad4 v dd ad3 v ss ad2 ad1 ad0 v dd int po1 po0 v ss sclk pi1 pi0 n. c. v ss mode1 mode0 s/dsel targ v dd init seloe v ss rstoe bsyoe dboe11 dboe10 dboe9 dboe8 idsel c/be3 ad24 ad25 v ss ad26 ad27 v dd ad28 ad29 v ss ad30 ad31 v dd preq gnt v ss reset pclk serr dboe12 dboe13 v ss dboe14 dboe15 udobep dboe0 dboe1 v dd dboe2 dboe3 dboe4 v ss dboe5 dboe6 dboe7 index
6 MB86606A n pin list (continued) pin no. 16-bit bus mode pci bus i/f mode pin no. 16-bit bus mode pci bus i/f mode mode 0 (68 i/f) mode 1 (80 i/f) mode 3 (pci i/f) mode 0 (68 i/f) mode 1 (80 i/f) mode 3 (pci i/f) i/o pin name i/o pin name i/o pin name i/o pin name i/o pin name i/o pin name 1 i/o dmd9 i/o ad23 31 v dd 2v ss 32 i/o d6 i/o ad11 3 i/o dmd8 i/o ad22 33 i/o d5 i/o ad10 4 i/o dmd7 i/o ad21 34 i/o d4 i/o ad9 5 i/o dmd6 i/o ad20 35 v ss 6v dd 36 i/o d3 i/o ad8 7 i/o dmd5 i/o ad19 37 i/o d2 i/o c/be0 8v ss 38 i/o d1 i/o ad7 9 i/o dmd4 i/o ad18 39 i/o d0 i/o ad6 10 i/o dmd3 i/o ad17 40 v ss 11 i/o dmd2 i/o ad16 41 i/o ldp i/o ad5 12 v ss 42 i uds ibhe i/o ad4 13 i/o dmd1 i/o c/be2 43 v dd 14 i/o dmd0 i/o frame 44 i lds iwr i/o ad3 15 i/o ldmdp i/o irdy 45 v ss 16 v ss 46 i r/w ird i/o ad2 17 i/o udp i/o trdy 47 i cs1 i/o ad1 18 v dd 48 i cs0 i/o ad0 19 i/o d15 i/o devsel 49 v dd 20 i/o d14 i/o stop 50 o/ od int 21 v ss 51 i a4 o po1 22 i/o d13 i/o perr 52 i a3 o po0 23 i/o d12 i/o par 53 v ss 24 i/o d11 i/o c/be1 54 i sclk 25 v ss 55 iu a2 iu pi1 26 i/o d10 i/o ad15 56 iu a1 iu pi0 27 i/o d9 i/o ad14 57 iu a0 iu n.c. 28 i/o d8 i/o ad13 58 v ss 29 i/o d7 i/o ad12 59 i mode1 30 v ss 60 i mode2
7 MB86606A (continued) (continued) pin no. 16-bit bus mode pci bus i/f mode pin no. 16-bit bus mode pci bus i/f mode mode 0 (68 i/f) mode 1 (80 i/f) mode 3 (pci i/f) mode 0 (68 i/f) mode 1 (80 i/f) mode 3 (pci i/f) i/o pin name i/o pin name i/o pin name i/o pin name i/o pin name i/o pin name 61 i s /dsel 91 i/o db7 62 o targ 92 i/o db6 63 v dd 93 v ss 64 o init 94 i/o db5 65 o seloe 95 i/o db4 66 v ss 96 i/o db3 67 o rstoe 97 i/o db2 68 o bsyoe 98 v ss 69 o dboe11 99 i/o db1 70 o dboe10 100 i/o db0 71 o dboe9 101 i/o udbp 72 o dboe8 102 v ss 73 v dd 103 i/o db15 74 i/o db11 104 i/o db14 75 i/o db10 105 i/o db13 76 i/o db9 106 i/o db12 77 v ss 107 v dd 78 i/o db8 108 o ldboep 79 i/o i/o 109 o dboe7 80 i/o req 110 o dboe6 81 i/o c/d 111 o dboe5 82 v ss 112 v ss 83 i/o sel 113 o dboe4 84 i/o msg 114 o dboe3 85 i/o rst 115 o dboe2 86 i/o ack 116 v dd 87 i/o bsy 117 o dboe1 88 v ss 118 o dboe0 89 i/o atn 119 o udboep 90 i/o ldbp 120 o dboe15
8 MB86606A (continued) i : input pin o : output pin i/o : input/output pin iu : input pin with pull-up resistor od : open-drain output pin pin no. 16-bit bus mode pci bus i/f mode pin no. 16-bit bus mode pci bus i/f mode mode 0 (68 i/f) mode 1 (80 i/f) mode 3 (pci i/f) mode 0 (68 i/f) mode 1 (80 i/f) mode 3 (pci i/f) i/o pin name i/o pin name i/o pin name i/o pin name i/o pin name i/o pin name 121 o dboe14 133 i dmlds idmwr i/o ad30 122 v ss 134 v ss 123 o dboe13 135 i dmr/w idmrd i/o ad29 124 o dboe12 136 i/o udmdp i/o ad28 125 i dma0 od serr 137 v dd 126 i tp i pclk 138 i/o dmd15 i/o ad27 127 i reset 139 i/o dmd14 i/o ad26 128 v ss 140 v ss 129 i dack ignt 141 i/o dmd13 i/o ad25 130 o dreq o preq 142 i/o dmd12 i/o ad24 131 v dd 143 i/o dmd11 i/o c/be3 132 i dmuds idmbhe i/o ad31 144 i/o dmd10 i idsel
9 MB86606A n pin description 1. scsi interface pin no. pin name i/o function 84, 81 89, 79 msg , c/d at n , i/o i/o these are the scsi control signal input and output pins. they can be connected directly to a single-ended scsi connector. either open-drain or totem pole output can be selected. 80, 86 req , ack i/o these are the scsi control signal input and output pins. they can be connected directly to a single-ended scsi connector. the output buffer is the totem pole type. 68 65 67 bsyoe seloe rstoe o these are used for output control of scsi control signals. they should be used as control signals for the external differential driver/receiver circuit. 87 83 85 bsy sel rst i/o these are the scsi control signal input and output pins. they can be connected directly to a single-ended scsi connector. the output buffer is the open-drain type. 120, 121, 123, 124, 69 to 72 119 109 to 111, 113 to 115, 117, 118 108 dboe15 to dboe8 udboep dboe7 to dboe0 ldboep o these are used for output control of scsi data bus signals. they should be used as control signals for the external differential driver/receiver circuit. 103 to 106, 74 to 76, 78 101 91, 92, 94 to 97, 99, 100 90 db15 to db8 udbp db7 to db0 ldbp i/o these are used to input and output scsi data bus signals. they can be connected directly to a single-ended scsi connector. either open-drain or totem pole output buffer can be selected. 64 62 init ta r g o these are used to output signals indicating the chip operating status. they should be used as control signals for the external differential driver/receiver circuit. 61 s /desl i this is used to input signal for selecting the chip operation mode. single-ended: input 0 differential-ended: input 1 while 0 is input to this pin, all the scsi control signals, data bus output control signals, init, and targ signals are fixed with l level. 54 sclk i this pin is used for a system clock input for scsi protocol controller block. (max. 40 mhz)
10 MB86606A 2. 16-bit bus mode-mpu interface pin no. pin name i/o function 48 cs0 i this is used to input signals for the mpu to select the spc as the i/o device. 47 cs1 i this is used to input select signals (external circuit select signals) for the mpu to input and output the dma data bus data via the spc. 19, 20, 22 to 24, 26 to 28 17 d15 to d8 udp i/o upper byte and parity of data bus when cs0 input valid: i/o ports for internal registers in spc when cs1 input valid: i/o ports for dma bus data 29, 32 to 34, 36 to 39 41 d7 to d0 ldp i/o lower byte and parity of data bus when cs0 input valid: i/o ports for internal registers in spc when cs1 input valid: i/o ports for dma bus data 51, 52, 55 to 57 a4 to a0 iu these are used to input addresses for selecting the internal registers. 46 rd (r/w )i in 80-series mode: this is used to input the read strobe signal for reading data from the spc to the mpu. in 68-series mode: this is used to input the r/w control signal for reading and writing data from the mpu to the spc. 44 wr (lds )i in 80-series mode: this is used to input the write strobe signal for writing data from the mpu to the spc. in 68-series mode: this is used to input the lds signal output by the mpu when the lower byte of the data bus is valid. 42 bhe (uds )i in 80-series mode: this is used to input the bhe signal output by the mpu when the upper byte of the data bus is valid. in 68-series mode: this is used to input the uds signal output by the mpu when the upper byte of the data bus is valid.
11 MB86606A 3. 16-bit bus mode C dma interface pin no. pin name i/o function 130 dreq o this is used to output dma transfer request signals to the dmac. dma data transfer between the spc and memory is requested. 129 dack i this is used to input dma-enabling signals from the dmac. when the dma enabling signal is active, dma reading and writing are executed. 138, 139, 141 to 144, 1, 3 136 dmd15 to 8 udmdp i/o upper byte and parity of dma data bus when cs1 input valid: the mpu data bus is directly connected. when 80-series mode: the 2nd data is input/output. when 68-series mode: the 1st data is input/output. 4, 5, 7, 9 to 11, 13, 14 15 dmd7 to 0 ldmdp i/o lower byte and parity of dma data bus when cs1 input valid: the mpu data bus is directly connected. when 80-series mode: the 1st data is input/output. when 68-series mode: the 2nd data is input/output. 135 dmrd (dmr/w )i in 80-series mode: this is used to input the iord or rd signal for outputting data from the spc to the dma bus. in 68-series mode: this is used to input the r/w control signal for outputting and inputting data from the dmac to the spc. 133 dmwr (dmlds )i in 80-series mode: this is used to input the iowr or wr signal for inputting data from the dma bus to the spc. in 68-series mode: this is used to input the lds signal output by the dmac when the lower byte of the dma data bus is valid. 132 dmbhe (dmuds )i in 80-series mode: this is used to input the bhe signal output by the dmac when the upper byte of the dma data bus is valid. in 68-series mode: this is used to input the uds signal output by the dmac when the upper byte of the dma data bus is valid. 125 dma0 i this is used to input the address data a0 signal output by the dmac in the 80-series mode. in 68-series mode: connect to power supply pin (v dd ). 126 tp (transfer permission) i this is used to input dma-transfer-enabling signals. when the tp signal is active, the spc performs the dma transfer. when this signal becomes inactive during dma transfer, the transfer stops temporarily at the block boundary.
12 MB86606A 4. pci bus interface mode pin no. pin name i/o function 130 preq o this pin is used to request the bus arbiter for use of the bus. 129 gnt i this is the response signal input pin to the req signal from the bus arbiter. 132, 133, 135, 136, 138, 139, 141, 142, 1, 3 to 5, 7, 9 to 11, 26 to 29, 32 to 34, 36, 38, 39, 41, 42, 44, 46 to 48 ad31 to ad0 i/o pci 32-bit address and data multiplexed pins 143, 13, 24, 37 c/be3 to c/be0 i/o bus command and byte enable signals multiplexed pins. 23 par i/o this is an even parity signal pin for the ad31 to ad0 and c/ be3 to c/be0 signals. this par signal becomes valid after one clock. 14 frame i/o this is a frame signal pin that indicates data are transferring on the bus. 17 trdy i/o data ready signal of target side. 15 irdy i/o data ready signal of initiator (bus master) side. 20 stop i/o this is a stop request signal to stop the data transfer from target to master. 19 devsel i/o device select pin. while the device is a target, this pin outputs the select signal that indicates the self device is selected. while the device is a master this pin functions as an input pin to indicate that a device on the bus is selected. 144 idsel i this is a chip select signal that indicates the configuration access. 126 pclk i pci bus clock input pin. the maximum clock frequency is 33 mhz. 22 perr i/o data parity error input and output pin. 125 serr od address parity error output pin.
13 MB86606A 5. other signals i : input pin o : output pin i/o : input and output pin od : open-drain output pin iu : input pin with pull-up resistor pin no. pin name i/o function 127 reset o this pin is used to input system reset signals. 59, 60 mode1, mode0 i these pins are used for setting the device operation mode as listed in the table below. 50 int o/ od interrupt output pin. either totem pole or open-drain output buffer can be selected. this pin has an internal pull-up resistor. 6, 18, 31, 43, 49, 63, 73, 107, 116, 131, 137 v dd power supply pin 2, 8, 12, 16, 21, 25, 30, 35, 40, 45, 53, 58, 66, 77, 82, 88, 93, 98, 102, 112, 122, 128, 134, 140 v ss ground pin 51, 52 po1, po0 o general purpose output ports that can control the external active scsi bus terminator etc. initial signal level on each pin is l. those pins are available only for pci bus interface mode. 55, 56 pi1, pi0 iu general purpose input ports. available only for pci bus interface mode. 57 n.c. no connection and unused pins. these pins exist on the only pci bus mode. these are internally pulled-up, and do not connect to the pins. mode1 mode0 operation mode 0 0 16-bit bus mode (68 series mode) 0 1 16-bit bus mode (80 series mode) 10reserved 1 1 pci bus interface mode
14 MB86606A n block diagram 1. 16-bit bus mode transfer controller msg c/d i/o atn bsyoe bsy seloe sel rstoe rst req ack init targ db15 to 8, udbp db7 to 0, ldbp dboe15 to 8, udboep dboe7 to 0, ldboep s/dsel scsi interface 1 2 3 4 5 6 7 8 9 internal processor phase controller various registers (32 bytes) (32 bytes) (2048 bytes) timer receive msg, cmd, status buffer send msg, cmd, status buffer user program memory data register dreq dack dmbhe (dmuds) dma0 dmd15 to 8, udmap dmd7 to 0, ldmdp iowr (dmlds) iord (dmr/w) tp dma interface wr (lds) rd (r/w) cs0 cs1 a4 to 0 bhe (uds) int d15 to 8, udp d7 to 0, ldp mpu interface (512 bytes)
15 MB86606A 2. pci bus interface mode par frame trdy irdy stop devsel perr serr idsel pclk preq gnt ad31 to 0 c/be3 to 0 pci interface 11 10 burst-fifo (64 bytes) dma controller msg c/d i/o atn bsyoe bsy seloe sel rstoe rst req ack init targ db15 to 8, udbp db7 to 0, ldbp dboe15 to 8, udboep dboe7 to 0, ldboep s/dsel scsi interface transfer controller 1 2 3 4 5 6 7 8 9 internal processor phase controller various registers (32 bytes) (32 bytes) (2048 bytes) timer receive msg, cmd, status buffer send msg, cmd, status buffer user program memory data register (512 bytes)
16 MB86606A n block functions 1. internal processor this processor provides the sequence control between each phase. 2. timer this timer manages the time specified by scsi and the following time: ? req/ack assertion time for data at asynchronous transfer ? selection/reselection retry time ? selection/reselection timeout time ? req/ack timeout time during transfer asynchronous transfer (target) : time required for initiator to assert ack signal after asserting req signal asynchronous transfer (initiator) : time required for target to negate req signal after asserting ack signal synchronous transfer (target only) : time required for target to receive ack signal for setting offset value to 0 from initiator after sending req signal 3. phase controller this controller controls the arbitration, selection/reselection, data-in/out, command, status, and message-in/out phases executed on the scsi bus. 4. transfer controller this controller controls the information (data, command, status, message) transfer phases executed on the scsi bus. there are two types of transfer for executing the information transfer phases. ? asynchronous transfer : control by interlocking req and ack signals ? synchronous transfer : control with maximum of 32-byte offset value in data-in/out phase depending on the data migration, there are the following two modes. ? program transfer : performed via mpu interface using data registers ? dma transfer : performed via dma interface using dreq and dack pins at synchronous transfer, the transfer parameters (transfer mode, minimum cycle period of req or ack signal sent from spc in synchronous transfer, and maximum value between req and ack signals in synchronous transfer) can be saved for each id and are automatically set when the data phase is started. the transfer byte count is determined by block length number of blocks. 5. various registers ? command register this register specifies each command with an 8-bit code. when using the user program, specify 1 at the bit 7. the lower 7 bits (bit 6 to bit 0) are invalid. ? nexus status register this register indicates the chips operating condition, the nexused partners id, and data register status. ? scsi control signal status register this register indicates the status of scsi control signals.
17 MB86606A ? interrupt status register this register indicates the interrupt status with an 8-bit code. ? command step register this register indicates the execution status of each command with an 8-bit step code. error causes can be analyzed by referencing the interrupt status register and this register. ? group 6/7 command length setting register this register sets the group 6/7 command length not defined in the scsi standard. setting this register determines the group 6/7 command length. 6. receive msg, cmd, status buffer (receive mcs buffer) this is a 32-byte receive-only information buffer that holds the information for the message, command, and status received from the scsi bus. 7. send msg, cmd, status buffer (send mcs buffer) this is a 32-byte send-only information buffer that holds the information for the message, command, and status sent on the scsi bus. 8. user program memory this is a 2048-byte program memory that stores programmable commands. it can consist of 1024-byte 2 banks or 2048-byte 1 bank. 9. data register this is a 512-byte fifo data register that holds data in the data phase executed on the scsi bus. 10.burst fifo 64-byte fifo type data buffer to perform burst transfer during the pci bus interface mode. the device has total 576-byte fifo with data register and burst fifo in the pci bus interface mode. 11.dma controller this is a 32-bit dma controller that performs data transfer. this dmac is a bus master during the pci bus interface mode.
18 MB86606A n absolute maximum ratings * : the voltages are based on v ss (= 0v) note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n recommended operating conditions * : the voltages are based on v ss (= 0v) note: the recommended operating conditions are the recommended values for assuring normal logic operation of the lsi. requirements in electrical characteristics (dc and ac characteristics) are assured within the range of the recommended operating conditions. parameter symbol rating unit min. max. supply voltage* v dd v ss C0.5 6.0 v input voltage* v i v ss C0.5 v dd +0.5 v output voltage* v o v ss C0.5 v dd +0.5 v operating ambient temperature top C25 +85 c storage temperature tstg C40 +125 c parameter symbol value unit min. typ. max. supply voltage* v dd 4.75 5.0 5.25 v scsi clock input frequency f scsi 20.0 40.0 mhz pci clock input frequency f pci 33.0 mhz operating temperature ta 0 +70 c
19 MB86606A n electrical characteristics 1. dc characteristics (v dd = +5 v 5%, v ss = 0 v, ta = 0 to +70 c) 3st. : three-state mode *1 : scsi pins are; udbp , db15 to db8 , ldbp , db7 to db0 , bsy , sel , rst , atn , req , ack , msg , c/d and i/o . (total 27 pins) *2 : leak current when the three-state output pin output and the bidirectional bus pin output are in a high impedance state. parameter symbol condition value unit min. max. input voltage* 1 scsi pins v ih 1.9v v il 1.0v sclk pins sdsel pins v ih 2.4v v il 0.8v other pins v ih 2.0v v il 0.8v scsi-pin input hysteresis* 1 v hw 0.3v output voltage* 1 scsi pins in single- end mode req , ack v oh i oh = C7.0 ma 2.0 3.24 v v ol i ol = +48.0 ma 0.5 v rst , bsy , sel v ol i ol = +48.0 ma 0.5 v others non-3st. v ol i ol = +48.0 ma 0.5 v 3st. v oh i oh = C7.0 ma 2.0 3.24 v v ol i ol = +48.0 ma 0.5 v in differential mode v oh i oh = C7.0 ma 2.0 3.24 v v ol i ol = +3.2 ma 0.4 v pci bus interface pins v oh i oh = C2.0 ma 4.2 v v ol i ol = +6.0 ma 0.55 v other pins v oh i oh = C2.0 ma 4.2 v v ol i ol = +3.2 ma 0.4 v input leakage current i li v in = 0 to v dd C10 +10 m a input/output leakage current* 2 i loz v in = 0 to v dd C10 +10 m a supply current i dd 150ma
20 MB86606A 2. input/output pin capacitance (v dd = v in = 0 v, f = 1 mhz, ta = +25 c) 3. load conditions for measurement of ac characteristics (1) non-scsi pins (v dd = +5 v 5%, v ss = 0 v, ta = 0 to +70 c) (2) scsi pins (v dd = +5 v 5%, v ss = 0 v, ta = 0 to +70 c) parameter pin name symbol conditions unit min. max. input-pin capacitance sclk, pclk (tp) c in 12pf other input pins 8 pf output-pin capacitance c out 10pf input/output-pin capacitance non-scsi pins c i/o 10pf scsi pins 25 pf MB86606A measurement pin measurement point c l MB86606A measurement pin measurement point r l2 c l r l1 16-bit bus mode pci bus interface mode pin name c l int, dreq 60 pf d15 to d8, udp, d7 to d0, ldp, dmd15 to dmd8, udmdp, dmd7 to dmd0, ldmdp 85 pf pin name c l pci bus pins 50 pf load resistance r l1 = 110 w r l2 = 165 w load capacitance c l = 200 pf
21 MB86606A 4. ac characteristics (1) system clock ? scsi clock (sclk pin) note: when the internal operating clock frequency is the same as the input clock frequency, (when using the device in divide-by-1 mode), the clock pulse width for l and h levels must have minimum 20.0 ns or longer. (i.e. when the clock conversion register value is 0bh (address: 10h in the initial setting registers) and input clock frequency = 20 mhz.) parameter symbol value unit min. typ. max. clock period t clf 25.0 50.0 ns clock pulse width (low) t clch 10.0 ns clock pulse width (high) t chcl 10.0 ns clock pulse rise time t cr 5.0ns clock pulse fall time t cf 5.0ns sclk 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t cf t cr t clch t clf t chcl
22 MB86606A ? pci clock (pclk pin) (2) system reset parameter symbol value unit min. typ. max. clock frequency t pcy 30.0 ns clock pulse width (low) t plo 12.0 ns clock pulse width (high) t phi 12.0 ns clock slew rate t psr 1.0 4.0 v/ns clock amplitude v ihp C v ilp 2.0 v parameter symbol value unit min. typ. max. reset (reset ) pulse l level pulse width t wrsl 4 t clf ns pclk 2.0 v 0.8 v 2.0 v 0.8 v 2.0 v 0.8 v 2.0 v 0.8 v v ihp v ilp t phi t pcy t plo reset t wrsl
23 MB86606A 5. mpu interface (1) register write timing for 80 series parameter symbol value unit min. max. address (a4 to a0), bhe setup time (1) t aws 20 ns address (a4 to a0) hold time (1) t awh 10 ns address (a4 to a0), bhe setup time (2) t acs 10 ns address (a4 to a0) hold time (2) t ach 5ns cs0 setup time t cws 10 ns cs0 hold time t cwh 5ns data set up time t dws 25 ns data hold time t dwh 10 ns wr l level pulse width t wr 70 ns a4 to a0 bhe cs0 wr d15 to 8, udp d7 to 0, ldp t aws t awh t cwh t wr t cws t dwh t dws data t acs t ach
24 MB86606A (2) register read timing for 80 series parameter symbol value unit min. max. address (a4 to a0), bhe setup time (1) t ars 20 ns address (a4 to a0) hold time (1) t arh 10 ns address (a4 to a0), bhe setup time (2) t acs 10 ns address (a4 to a0) hold time (2) t ach 5ns cs0 setup time t crs 10 ns cs0 hold time t crh 5ns rd set low ? data output defined time t rld 40ns rd set high ? data output defined time t rhd 5ns rd pulse duration at low t rd 70 ns int signal clear time interrupt non-hold mode t dl 50ns interrupt hold mode t dl2 n?t clf +50 ns a4 to a0 bhe cs0 rd d15 to 8, udp d7 to 0, ldp t ars t arh t crh t rd t crs t rhd t rld t dl t dl2 * int int *: t dl2 is defined by the rising edge of strobe signal that reads out the step code for the last interrupt source. valid data (n is the division ratio) t acs t ach
25 MB86606A (3) register write timing for 80 series (for external access) parameter symbol value unit min. max. address (a0), bhe setup time (1) t awse 20 ns address (a0) hold time (1) t awhe 10 ns address (a0), bhe setup time (2) t acse 10 ns address (a0) hold time (2) t achd 5ns cs1 setup time t cwse 10 ns cs1 hold time t cwhe 5ns wr set low ? dma bus output delay time t whld 40ns wr set high ? dma bus output undefined time t whhd 5ns mpu data bus ? dma bus output delay time t dhd 20ns cs1 wr d15 to 8, udp d7 to 0, ldp t awse t awhe t cwhe t cwse t whhd t wlhd valid data data a0 bhe dmd15 to 8, udmdp dmd7 to 0, ldmdp t dhd t dhd t acse t achd
26 MB86606A (4) register read timing for 80 series (for external access) parameter symbol value unit min. max. address (a0), bhe setup time (1) t arse 20 ns address (a0), bhe hold time (1) t arhe 10 ns address (a0), bhe setup time (2) t acse 10 ns address (a0), bhe hold time (2) t achd 5ns cs1 setup time t crse 10 ns cs1 hold time t crhe 5ns rd set low ? mpu bus output enable time t rlnz 40ns rd set high ? mpu bus output disable time t rhhz 5ns dma data bus ? mpu bus output delay time t hdd 20ns cs1 rd d15 to 8, udp d7 to 0, ldp t arse t arhe t crhe t crse valid data a0 bhe t hdd t rlnz t rhhz data dmd15 to 8, udmdp dmd7 to 0, ldmdp t acse t achd
27 MB86606A (5) register write timing for 68 series parameter symbol value unit min. max. address (a4 to a0) setup time (1) t aws 20 ns address (a4 to a0) hold time (1) t awh 10 ns address (a4 to a0) setup time (2) t acs 10 ns address (a4 to a0) hold time (2) t ach 5ns cs0 setup time t cws 10 ns cs0 hold time t cwh 5ns data setup time t dws 25 ns data hold time t dwh 10 ns uds /lds l level pulse width t ds 70 ns r/w setup time t rws 10 ns r/w hold time t rwh 10 ns cs0 r/w d15 to 8, udp d7 to 0, ldp t aws t awh t cwh t cws data t dws t dwh a4 to a0 uds/lds t rwh t ds t rws t acs t ach
28 MB86606A (6) register read timing for 68 series parameter symbol value unit min. max. address (a4 to a0) setup time (1) t ars 20 ns address (a4 to a0) hold time (1) t arh 10 ns address (a4 to a0) setup time (2) t acs 10 ns address (a4 to a0) hold time (2) t ach 5ns cs0 setup time t crs 10 ns cs0 hold time t crh 5ns data output defined time t rld 40ns data output disable time t rhd 5ns uds /lds l level pulse width t ds 70 ns r/w setup time t rws 10 ns r/w hold time t rwh 10 ns int signal clear time t dh 50 ns t dh2 n?t clk +50 cs0 r/w d15 to 8, udp d7 to 0, ldp t ars t arh t crh t crs valid data t dh2 * a4 to a0 uds/lds t rhd t rld int int t rwh t ds t rws t dh (n is the division ratio) *: t dh2 is defined by the rising edge of strobe signal that reads out the step code for the last interrupt source. t acs t ach
29 MB86606A (7) register write timing for 68 series (for external access) parameter symbol value unit min. max. address (a0) setup time (1) t awse 20 ns address (a0) hold time (1) t awhe 10 ns address (a0) setup time (2) t acse 10 ns address (a0) hold time (2) t achd 5ns cs1 setup time t cwse 10 ns cs1 hold time t cwhe 5ns uds /lds set low ? dma bus output delay time t wlhd 40ns uds /lds set high ? dma bus output undefined time t whhd 5ns mpu data bus ? dma bus output delay time t dhd 20ns r/w setup time t rws 10 ns r/w hold time t rwh 10 ns cs1 r/w d15 to 8, udp d7 to 0, ldp t awse t awhe t cwhe t cwse data t wlhd t whhd uds/lds t rwh t ds t rws valid data t dhd dmd15 to 8, udmdp dmd7 to 0, ldmdp a0 t acse t achd
30 MB86606A (8) register read timing for 68 series (for external access) parameter symbol value unit min. max. address (a0) setup time (1) t arse 20 ns address (a0) hold time (1) t arhe 10 ns address (a0) setup time (2) t acse 10 ns address (a0) hold time (2) t achd 5ns cs1 setup time t crse 10 ns cs1 hold time t crhe 5ns uds /lds set low ? mpu data bus output enable time t rlnz 40ns uds /lds set high ? mpu data bus output disable time t rhh 5ns dma bus ? mpu data bus output delay time t hdd 20ns r/w setup time t rws 10 ns r/w hold time t rwh 10 ns cs1 r/w d15 to 8, udp d7 to 0, ldp t arse t arhe t crhe t crse uds/lds t rwh t rws valid data t rhhz dmd15 to 8, udmdp dmd7 to 0, ldmdp a0 t rlnz t hdd data t acse t achd
31 MB86606A 6. dma interface dma access timing the time regulations are not applicable in the following cases: ? during scsi input and when data buffer empty, or when one byte held ? during scsi output and when data buffer full, or when 511 bytes held ? when parity error detected (target) ? when error stopping transfer occurs in scsi interface (1) access cycle time (burst mode) parameter symbol value unit min. max. address cycle time t dcy1 2 t clf ns t dcy2 3 t clf ns t dcy3 4 t clf ns t dcy4 1 t clf ns t dcy2 iowr/iord dmuds/dmlds t dcy1 t dcy4 t dcy3
32 MB86606A (2) write timing (burst mode for 80 series) parameter symbol value unit min. max. dreq set high ? dack set low t dhal 0ns iowr set low ? dreq set low t aldl 25ns dreq set low ? dreq set high t dldh 0ns dack set low ? iowr set low t alwl 0ns dmbhe , dma0 setup time t daws 10 ns iowr l level pulse width t dwr 25 ns iowr set high ? dack set high t whah 0ns dmbhe , dma0 hold time t dawh 10 ns input data setup time t ddws 25 ns input data hold time t ddwh 5ns dack data dmbhe dma0 dreq dmd15 to 0 udmdp, ldmdp iowr t dhal t aldl t whah t dldh t dawh t ddwh t ddws t dwr t daws t alwl
33 MB86606A (3) read timing (burst mode for 80 series) parameter symbol value unit min. max. dreq set high ? dack set low t dhal 0ns iord set low ? dreq set low t aldl 25ns dreq set low ? dreq set high t dldh 0ns dack set low ? iord set low t alrl 0ns dmbhe , dma0 setup time t dars 10 ns iord l level pulse width t drd 25 ns iord set high ? dack set high t rhah 0ns dmbhe , dma0 hold time t darh 10 ns data output defined time t drld 25ns data output hold time t drhd 10 ns dack valid data dmbhe dma0 dreq dmd15 to 0 udmdp, ldmdp iord t dhal t aldl t dldh t rhah t darh t drhd t drld t drd t dars t alrl
34 MB86606A (4) write timing (burst mode for 68 series) parameter symbol value unit min. max. dreq set high ? dack set low t dhal 0ns dmuds /dmlds set low ? dreq set low t aldl 25ns dreq set low ? dreq set high t dldh 0ns dack set low ? dmuds /dmlds set low t aldl 5ns r/w setup time t drws 10 ns dmuds /dmlds l level pulse width t dds 25 ns dmuds /dmlds set high ? dack set high t dhah 0ns r/w hold time t drwh 10 ns input data setup time t ddws 25 ns input data hold time t ddwh 5ns dack data dmr/w dreq dmd15 to 0 udmdp, ldmdp dmuds/dmlds t aldl t dhah t drwh t dds t drws t dhal t aldl t dldh t ddwh t ddws
35 MB86606A (5) read timing (burst mode for 68 series) parameter symbol value unit min. max. dreq set high ? dack set low t dhal 0ns dmuds /dmlds set low ? dreq set low t aldl 25ns dreq set low ? dreq set high t dldh 0ns dack set low ? dmuds /dmlds set low t aldl 5ns r/w setup time t drws 10 ns dmuds /dmlds l level pulse width t dds 25 ns dmuds /dmlds set high ? dack set high t dhah 0ns r/w hold time t drwh 10 ns output data valid time t drld 25ns output data hold time t drhd 10 ns dack valid data dmr/w dreq dmd15 to 0 udmdp, ldmdp dmuds/dmlds t dhal t aldl t dldh t dhah t drwh t dds t drws t aldl t drld t drhd
36 MB86606A 7. pci interface (1) pci interface signal timing *1: applicable to preq pin *2: applicable to gnt pin parameter symbol value unit min. max. output signal valid time t pval 2 11/12* 1 ns output disable time t poff 28ns output enable time t pon 2ns input setup time t psu 7/10* 2 ns input hold time t phd 0ns pciclk output h to i or l to h output h/l to hi-z output hi-z to h/l input 1.5 v 0.4 v 2.4 v 1.5 v 1.5 v 2.4 v 0.4 v t pval t poff t pon t psu t phd 1.5 v
37 MB86606A (2) configuration register read timing (3) configuration register write timing pciclk frame idsel ad31 to 00 c/be3 to 0 irdy trdy devsel stop pciclk frame idsel ad31 to 00 c/be3 to 0 irdy trdy devsel stop note: for the access to the configuration register, only one data transfer possible. when a master device executes the burst transfer, a target device asserts stop signal, and performs the target termination.
38 MB86606A (4) basic control register read timing (target mode) ? byte or word access pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel stop note: only one data transfer is possible for reading basic control regisuter. when a master device does the burst transfer to the target device, it asserts stop signal and performs the target termination. burst read (target termination), single read
39 MB86606A ? long-word access pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel stop pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel stop note: for the read operation of basic control registers, only one data transfer possible. when a master device executes the burst transfer, a target device asserts stop signal and performs the target termination. single read burst read (target termination)
40 MB86606A (5) target mode C i/o, memory read timing (except basic control registers) ? byte, word access pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel single read burst read
41 MB86606A ? long-word access single read frame ad31 to 00 c/be3 to 0 irdy trdy devsel pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel pciclk burst read
42 MB86606A (6) target mode C i/o, memory write timing ? byte, word access pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel single write burst write
43 MB86606A ? long-word access pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel single write burst write
44 MB86606A (7) data read timing (master mode) ? burst length = 1 and 4 ? burst length = 8 ? burst length = 16 pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel burst = 1 burst = 4 pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel
45 MB86606A (8) data write timing (master mode) ? burst length = 1 and 4 ? burst length = 8 ? burst length = 16 burst = 1 burst = 4 pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel pciclk frame ad31 to 00 c/be3 to 0 irdy trdy devsel
46 MB86606A 8. scsi interface (1) initiator asynchronous input timing (target ? initiator) * : t racy (req set high ? ack set low) is defined as either longer time of (t raoh + t aohr +t raol ) or t racy itself note: time requirements in this section do not apply in the following cases; ? when data register full in data phase ? when last byte transferred parameter symbol value unit min. max. ack set low ? req set high t aolr 0ns req set high ? ack set high t raoh 60ns ack set high ? req set low t aohr 10 ns data bus valid ? req set low t dtsu 10 ns req set low ? data bus hold time t dhld 20 ns req set low ? ack set low t raol 40ns req set high ? ack set low* t racy 3 t clf +40 ns req ack db7 to 0, p db15 to 8, p data t dhld t aolr t raoh t aohr t raol t racy t dtsu
47 MB86606A (2) initiator asynchronous output timing (initiator ? target) * : the value of s varies with the setting condition of the asynchronous setup time register (address 17h). note: this output timing regulations are not applicable when the data register is empty in the data phase. parameter symbol value unit min. max. ack set low ? req set high t aolr 0ns req set high ? ack set high t raoh 60ns ack set high ? req set low t aohr 10 ns data bus output defined ? ack set low* t dvld s?t clf C10 ns req set high ? data bus hold time t divd 2 t clf ns req set low ? ack set low t raol 40ns req ack db7 to 0, p db15 to 8, p valid data valid data t aolr t raoh t aohr t raol t racy * t dvld t divd t dvld * : the time (t racy ) of req set high ? ack set low is defined by the longer time either (t raoh + t aohr +t raol ) or (t divd + t dvld ).
48 MB86606A (3) initiator synchronous transfer req /ack timing * : the values of a and n vary with the setting condition of the transfer period register (address 0ch). parameter symbol value unit min. max. ack assertion period* t akap a?t clf C4 ns ack negation period* t anap n?t clf C6 ns req assertion period t rqap 20 ns req negation period t rnap 20 ns req input cycle time (1) t rqf1 1 t clf ns req input cycle time (2) t rqf2 3 t clf ns ack req t rqap t rnap t akap t anap t rqf1 t rqf2
49 MB86606A (4) initiator synchronous transfer input timing (target ? initiator) (5) initiator synchronous transfer output timing (initiator ? target) * : the values of a and n vary with the setting condition of the transfer period register (address 0ch). parameter symbol value unit min. max. data bus defined ? req set low t dtsu 5ns req set low ? data bus hold time t dhld 15 ns parameter symbol value unit min. max. data bus defined ? ack set low* t dvak n?t clf C10 ns ack set low ? data bus hold time* t akdh a?t clf C5 ns req db7 to 0, p db15 to 8, p data data t dtsu t dhld t dtsu t dhld ack db7 to 0, p db15 to 8, p valid data valid data t dvak t akdh t dvak t akdh
50 MB86606A (6) target asynchronous input timing (initiator ? target) * : t racy (ack set low ? req set low) is defined as either longer time of (t aroh + t roha +t arol ) or t racy itself note: the input timing regulations are not applicable when the data register is full in the data phase. parameter symbol value unit min. max. req set low ? ack set low t rola 0ns ack set low ? req set high t aroh 60ns req set high ? ack set high t roha 0ns data bus defined ? ack set low t dtsu 10 ns ack set low ? data bus hold time t dhld 20 ns ack set high ? req set low t arol 40ns ack set low ? req set low* t racy 3 t clf + 40 ns req ack db7 to 0, p db15 to 8, p t aroh data t rola t roha t arol t racy t dhld t dtsu
51 MB86606A (7) target asynchronous input timing (target ? initiator) * : the value of s varies with the setting condition of the asynchronous setup time register (address 17h). note: the output timing regulations are not applicable when the data register is empty in the data phase. parameter symbol value unit min. max. req set low ? ack set low t rola 0ns ack set low ? req set high t aroh 60ns req set high ? ack set high t roha 0ns data bus defined ? req set low* t dvld s?t clf C 10 ns ack set low ? data bus hold time t divd 2 t clf ns ack set high ? req set low t arol 40ns req ack db7 to 0, p db15 to 8, p t aroh valid data valid data t rola t roha t arol t racy * t dvld t divd t dvld * : the time (t racy ) of ack set high ? req set low is defined by the longer time either (t aroh + t roha +t arol ) or (t divd + t dvld ).
52 MB86606A (8) target synchronous transfer req /ack timing * : the values of a and n vary with the setting condition of the transfer period register (address 0ch). parameter symbol value unit min. max. req assertion period* t rqap a?t clf C 4 ns req negation period* t rnap n?t clf C 6 ns ack assertion period t akap 20 ns ack negation period t anap 20 ns ack input cycle time (1) t akf1 1 t clf ns ack input cycle time (2) t akf2 3 t clf ns req ack t rqap t rnap t akap t anap t akf1 t akf2
53 MB86606A (9) target synchronous transfer input timing (initiator ? target) (10) target synchronous transfer output timing (target ? initiator) * : the values of a and n vary with the setting condition of the transfer period register (address 0ch). parameter symbol value unit min. max. data bus defined ? ack set low t dtsu 5ns ack set low ? data bus hold time t dhld 15 ns parameter symbol value unit min. max. data bus defined ? req set low* t dvrq n?t clf C 10 ns req set low ? data bus hold time* t rqdh a?t clf C 5 ns ack db7 to 0, p db15 to 8, p data data t dtsu t dhld t dtsu t dhld req db7 to 0, p db15 to 8, p valid data valid data t dvrq t rqdh t dvrq t rqdh
54 MB86606A (11) a, n, and s values in scsi interface timing specifications ? set value for transfer period register and a, n values note: the a and n values in the register setting represent the assertion and negation periods (in clock-cycle units). the numerical value is applicable to the a and n values in ac characteristics. transfer period register an transfer period register an 43210 43210 00001(inhibited)(inhibited)10001 9 8 00010 1 1 10010 9 9 00011 2 1 10011 10 9 00100 2 2 10100 10 10 00101 3 2 10101 11 10 00110 3 3 10110 11 11 00111 4 3 10111 12 11 01000 4 4 11000 12 12 01001 5 4 11001 13 12 01010 5 5 11010 13 13 01011 6 5 11011 14 13 01100 6 6 11100 14 14 01101 7 6 11101 15 14 01110 7 7 11110 15 15 01111 8 7 11111 16 15 10000 8 8 00000 16 16
55 MB86606A ? set value for asynchronous setup time register and s value note: the s (setup time) value of the setup time setting register in asynchronous data transfer represents the time required to assert the req or ack signal after setting data at the data bus (in clock-cycle units). the numerical value is applicable to the s value in ac characteristics. asynchronous setup time setting register s 3210 00011 00102 00113 01004 01015 01106 01117 10008 10019 101010 101111 110012 110113 111014 111115 000016
56 MB86606A n system configuration 1. 80-series separate bus type differential dr/rev MB86606A db15 to 8 udbp db7 to 0 dboe15 to 8 udboep dboe7 to 0 ack atn init req msg c/d i/o targ bsy bsyoe sel seloe rst rstoe sdsel ldbp ldboep clk reset mode0 int cs0 cs1 a4 to a0 bhe wr dreq tp mode1 rd dack dma0 dmd15 to 0 ldmdp udmdp dmbhe iowr iord d15 to d0 ldp udp osc reset circuit address decode dma control data buffer memory address address bus data bus dma bus mpu
57 MB86606A 2. 68-series separate bus type differential dr/rev MB86606A db15 to 8 udbp db7 to 0 dboe15 to 8 udboep dboe7 to 0 ack atn init req msg c/d i/o targ bsy bsyoe sel seloe rst rstoe sdsel ldbp ldboep clk reset mode0 int cs0 cs1 a4 to a1 r/w lds dreq tp mode1 uds dack dma0 dmd15 to 0 ldmdp udmdp dmr/w dmlds dmuds d15 to d0 ldp udp address address bus data bus dma bus a0 osc reset circuit address decode dma control data buffer memory mpu
58 MB86606A 3. 80-series common bus type differential dr/rev MB86606A db15 to 8 ldbp db7 to 0 dboe15 to 8 udboep dboe7 to 0 ack atn init req msg c/d i/o targ bsy bsyoe sel seloe rst rstoe sdsel udbp ldboep clk reset mode0 int cs1 cs0 a4 to a0 bhe wr dreq tp mode1 rd dack dma0 dmd15 to 0 ldmdp udmdp dmbhe iowr iord d15 to d0 ldp udp address bus data bus dma bus osc reset circuit address decode dma control mpu
59 MB86606A 4. 68-series common bus type differential dr/rev MB86606A db15 to 8 ldbp db7 to 0 dboe15 to 8 udboep dboe7 to 0 ack atn init req msg c/d i/o targ bsy bsyoe sel seloe rst rstoe sdsel udbp ldboep clk reset mode0 int cs1 cs0 a4 to a1 r/w lds dreq tp mode1 uds dack dma0 dmd15 to 0 ldmdp udmdp dmr/w dmlds dmuds d15 to d0 ldp udp address bus data bus dma bus a0 osc reset circuit address decode dma control mpu
60 MB86606A 5. example of connection in differential mode (example of driver/receiver connection) (top view) ro re de di 1 2 3 4 v cc do, ri do, ri gnd 8 7 6 5 r d mb561 MB86606A db15 to 0 udbp ldbp dboe15 to 0 udboep ldboep ack, atn req, msg c/d, i/o targ bsy, sel rst bsyoe, seloe rstoe sdsel init 18 18 2 4 3 3 r d r d r d r d (+) signal ( - ) signal scsi bus (+) signal ( - ) signal (+) signal ( - ) signal (+) signal ( - ) signal
61 MB86606A 6. example of connection in single-end mode MB86606A db15 to 0 udbp ldbp dboe15 to 0 udboep ldboep ack, atn req, msg c/d, i/o targ bsy, sel rst bsyoe, seloe rstoe sdsel init 18 18 2 4 3 3 scsi bus (open) (open) (open) (open)
62 MB86606A n ordering information part number package remarks MB86606Apmt2 144-pins, plastic lqfp (fpt-144p-m08)
63 MB86606A n package dimension c 1995 fujitsu limited f144019s-1c-2 details of "a" part details of "b" part 0.50?.20(.020?008) 0 10 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 22.00?.30(.866?012)sq 20.00?.10(.787?004)sq 0.20?.10 (.008?004) 0.08(.003) m 0.15?.05 (.006?002) 1.70(.67)max 0(0)min (stand off) 21.00 17.50 (.827) nom (.686) ref 0.10(.004) "a" "b" 36 37 72 73 108 109 144 1 index 0.50(.0197)typ lead no. (mounting height) dimensions in mm (inches) (fpt-144p-m08) 144-pin plastic lqfp
64 MB86606A fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9904 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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